Currently used integrated circuit (IC) fabrication methods commonly involve deposition of metals into recessed features formed in a layer of inter-layer dielectric (ILD). The deposited metal provides the conductive paths which extend horizontally and vertically within the IC substrate, connecting the active devices (e.g., transistors) in a desired pattern. The metal lines formed in adjacent ILD layers are connected to each other by a series of interconnections (interconnects). On a typical wafer substrate, one or several layers of dielectric are deposited onto a layer containing the active devices, and are patterned to provide vertical and horizontal recessed features (vias and trenches) which are subsequently filled with metal. The resulting layer containing metal-filled lines residing in a dielectric is referred to as a metallization layer. Next, a second metallization layer is similarly formed on top of the first metallization layer and interconnects are formed between the two metallization layers. A stack containing several metallization layers which are electrically connected to each other by a plurality of interconnects, can be similarly formed using this process flow. The described process, known as Damascene processing, is particularly advantageous when copper is used as a metallization metal, because copper is not easily amenable to plasma etching, and therefore cannot be easily patterned. Copper is a commonly used metal in modern devices due to its low resistivity and high electromigration resistance. Aluminum is another frequently used metallization metal.
With the miniaturization of IC devices, the dimensions of the device features have dramatically decreased. Specifically, the widths of the recessed features in current IC devices are typically less than 200 nm, often less than 100 nm. Filling of these recessed features with metals presents many challenges. In particular, the difficulty of depositing metals into narrow recesses without forming microvoids or defects, has prevented the use of PVD methods for metal gap fill at a current level of miniaturization. In the case of copper, the copper fill is currently accomplished by depositing a thin conformal copper seed layer by PVD, followed by deposition of a bulk amount of copper by electroplating. The seed layer serves as an electrical contact on a wafer during electroplating.
For some applications, it is preferable to minimize process steps, in order to decrease processing times and production costs. Specifically, the ability to perform PVD-only metal fill would be desirable.
However, the goal of PVD-only metal fill has been difficult to attain. The majority of currently known methods for PVD metal fill are applicable only to metal deposition in very wide and shallow features. With the use of conventional PVD in narrow and high aspect ratio features, the metal sputtered from the metal target tends to accumulate at the opening of the recessed feature, causing formation of overhangs, and, ultimately, leading to formation of voids within the filled feature.
Currently, there is a need for PVD-based methods that would allow for partial or complete metal fill in relatively narrow features without formation of voids. For certain applications, such methods may completely eliminate the necessity for wet processing (e.g., electroplating). Further, such methods may eliminate the need for subsequent CMP removal of the metal from the field, further improving efficiency of IC fabrication.